10h–1Fh Register Map Detailed DescriptionBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 528
1Ch: TDR Control 1 Register (Shadow Register Selector = “06h”
1Ch: TDR Control 2 Register (Shadow Register Selector = “07h”)
0 CLK125 OUTPUT
ENABLE
RW 1 = enable CLK125 output
0 = disable CLK125 output
1
Bit Name RW Description Default
15 WRITE ENABLE RW 1 = write bits [9:0]
0 = read bits [9:0]
0
14:10 SHADOW REGISTER
SELECTOR
RW Shadow Register Selector 00110
9 SPARE RW write as 0, ignore on read 0
8 TDR LINK TIME OUT R tdr linkpulse time out status 0
7:5 TEST PULSE SIZE RW size of test pulse in increments of 8 ns. minimum
value = 1.
001
4:3 TX CHANNEL SEL RW channel to transmit test pulse 00
2:1 RX CHANNEL SEL RW channel to receive test data 00
0 TDR START/DONE RW
SC
write:
1: tdr start. self clearing
read:
1: tdr done status
0
Bit Name RW Description Default
15 WRITE ENABLE RW 1 = write bits [9:0]
0 = read bits [9:0]
0
14:10 SHADOW REGISTER
SELECTOR
RW Shadow Register Selector 00111
9:8 SPARE RW write as 0, ignore on read 00
7 PHASE STATUS R phase status 0
6 PHASE STATUS CLEAR RW 1: clear phase status on bit 7 0
5 FASTTIMERS RW 1: enable fasttimers 0
4 FEXT RW 1: enable fext mode
0: disable fext mode
0
3 MASTER RW 1: master mode
0: slave mode
0
2 EXTERNAL PHY NO
AUTO-NEG
RW 1: tdr test with external phy without auto-
negotiation
0: tdr test with external phy with auto-
negotiation
0
(Cont.)
Bit Name RW Description Default