Broadcom NetXtreme/NetLink BCM5718 Series

Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 386
Clock Speed Override Policy Register (offset: 0x3624)
Clock Override Enable Register (offset: 0x3628)
This register is reset by POR Reset or CPMU Register Software Reset. *The Force Disable bit has higher priority
than Override Enable.
Name Bits Access
Default
Value
Description
MAC Clock Speed Override
Enable
31 RW 0x0 Enable MAC clock speed override*.
Note: For 5719 and 5720 only
Reserved 30:21 DC 0x000 –
MAC Clock Switch 20:16 RW 00000 Software Controlled MAC Core Clock Speed
Select
00000: Core = 62.5 MHz (NCSI DLL/2)
10001: Core = 12.5 MHz (CK25/2)
10011: Core = 6.25 MHz (CK25/4)
10101: Core = 3.125 MHz (CK25/8)
10111: Core = 1.563 MHz (CK25/16)
For 5718
Software Controlled MAC Core Clock Speed
Select00000: Core = 62.5MHz (GPHY DLL/2)
00001: Core = 60.0 MHz (Alt Source/2)
00011: Core = 30.0 MHz (Alt Source/4)
00101: Core = 15.0 MHz (Alt Source/8)
00111: Core = 7.5M Hz (Alt Source/16)
01001: Core = 3.75 MHz (Alt Source/32)
10001: Core = 12.5 MHz (CK25/2)10011: Core =
6.25MHz (CK25/4)10101: Core = 3.125 MHz
(CK25/8)10111: Core = 1.563 MHz (CK25/
16)11001: Core = 781 KHz (CK25/32)
11111: Core = 12.5 MHz/1.25 MHz (MII_CLK/2)
Reserved 15:0 DC 0x0 –
Name Bits Access
Default
Value
Description
Reserved 31:14 DC 0x0 –
MAC Clock Speed Override
Enable
13 RW 0x0 Enable MAC clock speed override*.
1: Enable
0: Disable
APE Clock Speed Override
Enable
12 RW 0x0 Enable APE clock speed override*.
1: Enable
0: Disable