Data Structure and Register Changes for IOVBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 265
MSI-X Vectors Changes
The NetXtreme
®
I offers two vector modes within the MSI-X mode for IOV:
• Single Vector IOV mode (Restrict to Vector#0)
• Multivector IOV mode (17 Vectors Requested)
For more information, see “MSI-X” on page 240.
Register Changes
The following register changes have been made:
• GRC-MODE-REG (Offset 0x6800): Additional bits have been added to this existing register (see “Mode
Control Register (offset: 0x6800)” on page 468).
• RDI-MODE-REG (Offset 0x2400): Additional bits have been added to this existing register (see “Receive
Data and Receive BD Initiator Mode Register (offset: 0x2400)” on page 362).
• Standard Replenish LWM Register (Offset: 0x2D00): This register is meaningful in both Legacy and IOV
Modes (see “Standard Replenish LWM Register (offset 0x2D00)” on page 373).
• Jumbo Replenish LWM Register (Offset 0x2D04): This register is meaningful in both Legacy and IOV
Modes (see “Jumbo Replenish LWM Register (offset 0x2D04)” on page 374).
• BD Fetch Limit Register (Offset 0x2D08): This register is meaningful only in the IOV-Mode (see “BD Fetch
Limit Register (Offset 0x2D08)” on page 375).
• VRQ Status Register (Offset: 0x240C): Additional bits have been added to this existing register (see “VRQ
Status Register (offset: 0x240C)” on page 364).
• VRQ Flush Control Register (Offset: 0x2410): Additional bits have been added to this existing register (see
“VRQ Flush Control Register (Offset: 0x2410)” on page 364).
• VRQ Flush Timer Register (Offset: 0x2414): The description has been updated on this existing register
(see “VRQ Flush Timer Register (offset: 0x2414)” on page 365).
• HC Parameter Set Reset Register (Offset: 0x3C28): This parameter should be placed in this HC block (see
“HC Parameter Set Reset Register (Offset: 0x3C28)” on page 421).
• Perfect Match Destination Address Registers: Twenty additional Perfect Match Destination Address
Registers are added in RX-EMAC for VRQ Filtering purposes (see “Perfect Match Destination Address
Registers” on page 459).
• VRQ Filter Set Registers: The filter block can be programed via a new set of registers (see “VRQ Filter Set
Registers” on page 455).
• SEND_BD_INITIATOR_MODE_REG (Offset 0x1800) Additional bits have been added to this existing
register (see “Send BD Initiator Mode Register (offset: 0x1800)” on page 353).
• SEND_BD_FETCH_THRESHOLD_REG (Offset: 0x1850) This is a newly added register (see “Send BD
Fetch Threshold Register (offset: 0x1850)” on page 355).
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