Memory Arbiter Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 427
Memory Arbiter Status Register (offset: 0x4004)
Enable 1 RW 1 This bit controls whether the Memory Arbiter is
active or not. When set to 0, it completes the
current operation and cleanly halts. Until it is
completely halted, it remains 1 when read.
Reset 0 RW 0 When this bit is set to 1, the Memory Arbiter state
machine is reset. This is a self-clearing bit.
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
DMAW 2 Addr Trap 20 W2C 0 DMA Write 2 Memory Arbiter request trap.
Reserved 19:17 RO 0 –
SDI Addr Trap 16 W2C 0 Send Data Initiator Memory Arbiter request trap.
Reserved 15:13 RO 0 –
RDI2 Addr Trap 12 W2C 0 Receive Data Initiator 2 Memory Arbiter request
trap.
RDI1 Addr Trap 11 W2C 0 Receive Data Initiator 1 Memory Arbiter request
trap.
RQ Addr Trap 10 W2C 0 Receive List Placement Memory Arbiter request
trap.
Reserved 9 RO 0 –
PCI Addr Trap 8 W2C 0 PCI Memory Arbiter request trap.
Reserved 7 RO 0 –
RX RISC Addr Trap 6 W2C 0 RX RISC Memory Arbiter request trap.
DMAR1 Addr Trap 5 W2C 0 DMA Read 1 Memory Arbiter request trap.
DMAW1 Addr Trap 4 W2C 0 DMA Write 1 Memory Arbiter request trap.
RX-MAC Addr Trap 3 W2C 0 Receive MAC Memory Arbiter request trap.
TX-MAC Addr Trap 2 W2C 0 Transmit MAC Memory Arbiter request trap.
Reserved 1:0 RO 0 –
Name Bits Access
Default
Value
Description
To Next Page
Loading...
Need help?
General
