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Broadcom NetXtreme/NetLink BCM5718 Series - Memory Mapped I;O Registers; Figure 41: PCI Command Register; PCI Base Address Register; PCI Command Register

Broadcom NetXtreme/NetLink BCM5718 Series
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Configuration SpaceBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 184
Memory Mapped I/O Registers
The following Ethernet controller registers are used in the mode configuration of the PCI memory-mapped I/O.
PCI Command Register
The PCI_Command register is 16-bits wide (see Figure 41). The Ethernet controller does not have I/O mapped
I/O. The I/O_Space bit is deasserted by hardware. The Ethernet controller does support
Memory_Mapped_Memory and hardware will assert the Memory_Space bit. Both these bits are read-only and
are usually read by the PnP BIOS/OS. The BIOS/OS examines these bits to assign non-conflicting resources
to PCI devices.
Figure 41: PCI Command Register
PCI State Register
The PCI_State register is 32-bits wide. Operating mode is set with the Flat_View bit in the PCI_State register.
When the Flat_View bit is asserted, the Ethernet controller decodes a 32M of block host memory. When the
Flat_View bit is deasserted, the Ethernet controller decodes a 64K block of host memory.
PCI Base Address Register
The PCI_Base_Address Register (BAR) specifies the location of a Ethernet controller memory mapped I/O
block. The Ethernet controller mode configuration (Flat vs. Standard) affects how the BAR is setup (see
Figure 42 on page 185).
Bits 4–31 in the PCI_Base_Address register are selectively programmable based on the amount of host
memory requested. The PnP BIOS/OS will use an algorithm to test the BAR bits and determine the amount
of physical memory requested.
The Memory_Space_Indicator bit designates whether the BAR is memory or I/O mapped. The Ethernet
controller hard codes the Memory_Space_Indicator bit to zero (deasserted).
The Location/Type bits specify locations in host memory space where a device can decode physical
addresses. The Ethernet controller memory mapped I/O range may be placed anywhere in 64-bit address
space (Type = 10).
The Ethernet controller deasserts the Prefetchable bit to indicate that the memory range should not be
cached.
Mem I/O
I/O Space
Read Only
Always = 0
[0]
Bus
Mast
Spec
Cycle
Write
Invld
VGA
Snoop
Parity
Error
Step
Ctrl
Sys
Err
Fast
Back 2
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Rsvd
[1][2][3][7] [6] [5] [4][9] [8][15:10]
Memory Space
Read/Write

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