Bus InterfaceBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 186
Bus Interface
Description
The read/write DMA engines both drive the PCIe interface. Typically, each DMA engine alternates bursts to the
PCIe bus, and both interfaces may have outstanding transactions on the PCI bus. The BCM5718 family
architecture identifies two channels—a read DMA channel and a write DMA channel. Each channel corresponds
to the appropriate DMA engine (see Figure 44). The configuration of the DMA engines and the PCI interface is
discussed in this section.
Figure 44: Read and Write Channels of DMA Engine
The following architectural components are involved in the configuration of the PCI/DMA interface:
• DMA read engine
• DMA write engine
• DMA read FIFO
• DMA write FIFO
•PCIe interface
• PCI state register
• DMA read/write register
PCI Interface
Write FIFO Read FIFO
DMA Write
Engine
DMA Read
Engine
Write ChannelRead Channel
PCIe Bus
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