SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 552
AUTONEGADV
Register Description: Auto-negotiation capability register.
Register Offset: 0x4 at Block 0
0 EXT_CAPABILITY RO Extended capability
0 = Supports basic register set only
1 = Extended register capabilities supported
1
Table 128: 02h: PHY_Identifier_MSB_Register
Bits Name RW Description Default
15:0 OUI_MSB RO Bits 3:18 of organizationally unique identifier 0143h
Table 129: 03h: PHY_Identifier_LSB_Register
Bits Name RW Description Default
15:10 OUI_MSB RO Bits 3:18 of organizationally unique identifier 101111
9:4 MODEL RO Device Model number 111111
3:0 REVISION RO Device revision number 0000
Table 130: AUTONEGADV
Bits Name RW Description Default
15 NEXT_PG RO Next page 0
14 RESERVED RO Reserved write 0, ignore read 0
13:12 RF RW Remote fault
2’b00 = No fault
2’b01 = Link failure
2’b10 = Offline
2’b11 = Auto-negotiation error
0x0
11:9 RESERVED RO Reserved write 0, ignore read 0x0
8:7 PAUSE RW Pause
2’b00 = No pause
2’b01 = Asymmetric pause
2’b10 = Asymmetric pause towards link partner
2’b11 = Both symmetric and asymmetric pause, towards
local device
0x0
Table 127: MII Status (Cont.)
Bits Name RW Description Default
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