GRC RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 474
RX-CPU Timer Reference Register (offset: 0x6814)
The Timer Reference register allows the RX-RISC to receive an event when the free-running Timer register
counts up to this value.
RX-CPU Semaphore Register (offset: 0x6818)
The RX-RISC Semaphore register allows access to both internal RISC processors to a hardware semaphore
mechanism. Writes to the register indicates the preference to toggle the own/not own states of a single
semaphore bit. Reads of this register provide a 1 if that register owns the semaphore, and a 0 otherwise. To
obtain the semaphore, the normal operation is a loop containing a write 0 followed by a read. Exit the loop when
the read returns nonzero. To release the semaphore,
Recv List Selector 4 RO 0 Receive List Selector is nonzero.
SW Event 3 3 RW 0 SW Event 3 is set
Recv List Placement 2 RO 0 Receive List Placement FTQ has stalled.
SW Event 1 1 RW 0 SW Event 1 is set
SW Event 0 0 RW 0 SW Event 0 is set
Name Bits Access
Default
Value
Description
RX-CPU Timer Reference 31:0 RW 0 RX-RISC Timer Event when time stamp = RX-
RISC Timer Reference.
Name Bits Access
Default
Value
Description
Reserved 31:1 RO 0 –
RX-CPU Semaphore 0 RW 0 RX-CPU Semaphore
Name Bits Access
Default
Value
Description
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