10h–1Fh Register Map Detailed DescriptionBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 511
13h: False_Carrier_Sense_Counter_Register
14h: Local_Remote_Receiver_NOT_OK_Counters_Register
Make 100BASE-TX local receiver status signal and front end reset that works more like 1000BASE-T (no drop
in link unless maxwait_timer expires). Use this counter to replace the watchdog timeout count used in 5203 PHY
status register.
18h: Auxiliary Control Register (Shadow Register Selector = “000”)
Bit Name RW Default Description
15:8 SERDES_BER_COUNTER RO 00h Number of invalid code groups received while
sync_status = 1 since last cleared.
Cleared by writing expansion register 4D bit 15 =
1
7:0 FALSE_CARRIER_SENSE_COU
NTER
# (TX ERROR COUNTER)
RW
CR
00h Number of false carrier sense events since last
read. Counts packets received with transmit error
codes when TXERVIS bit in test register is set.
Freezes at FFh.
(Counts SerDes errors when register 1ch
shadow “11011” bit 9 = 1 otherwise copper
errors)
Bit Name RW Default Description
15:8 LOCAL_RECEIVER_NOT_OK_COUNT
ER
RW
CR
00h number of times local receiver status was
not OK since last read. Freezes at FFh.
7:0 REMOTE_RECEIVER_NOT_OK_
COUNTER
RW
CR
00h number of times remote receiver status was
not OK since last read. Freezes at FFh.
15:0 CRC_ERROR_COUNTER RW
CR
0000h when CRC error count visibility test mode is
set, this reg becomes a 16 bit CRC error
counter. Freezes at FFFFh.
(Counts SerDes errors when register 1ch
shadow “11011” bit 9 = 1 otherwise copper
errors)
Bit Name RW Description Default
15 EXTERNAL LOOPBACK RW 1 = external loopback enabled
0 = normal operation
0
14 EXTENDED PACKET
LENGTH
RW 1 = allow reception of extended length packets
(GBIC)
0 = allow normal length Ethernet packets only
0
13:12 EDGERATE CONTROL
(1000T)
(LSB or’ed with ER pin)
RW 00 = 4.0ns (1000T)
01 = 5.0ns (1000T)
10 = 3.0ns (1000T)
11 = 0.0ns (1000T)
00
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