10h–1Fh Register Map Detailed DescriptionBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 512
11 ENABLE SM_DSP
CLOCK
RW 1 = Clock is enabled.
0 = Clock is gated off.
0
10 TRANSMIT 6dB CODING RW 1 = transmit using 6dB coding
0 = transmit using 3dB coding
1
9:8 RECEIVE SLICING RW 00 = normal Viterbi/DFE MLSE
01 = 4D symbol by symbol slicing for 3 dB option
10 = 3 level 1D symbol by symbol slicing
11 = 5 level 1D symbol by symbol slicing during
SEND IDLE/DATA, 3 level else
00
7 DISABLE PARTIAL
RESPONSE FILTER
RW 1 = transmitter partial response filter disabled
0 = transmitter partial response filter enabled
0
6 DISABLE INVERSE PRF RW 1 = receiver inv. partial response filter disabled
(overrides Phy Control and other MII register
settings if disabled)
0 = receiver inv. partial response filter enabled
0
5:4 EDGERATE CONTROL
(100TX)
(LSB or’ed with ER pin)
RW 00 = 4.0 ns (100TX)
01 = 5.0 ns (100TX)
10 = 3.0 ns (100TX)
11 = 0.0 ns (100TX)
00
3 DIAGNOSTIC MODE RW 1 = When convergence fails, hold in failed state
until cleared
0 = Normal operation, retrain on failure
0
2:0 SHADOW REGISTER
SELECTOR
(These bits are written
on all writes to 18h
regardless of the value)
RW 000 = Normal operation
001 = 10 BASE-T register
010 = Power Control register
011 = IP Phone register
100 = Misc Test register 1
101 = Misc Test register 2
110 = Manual IP Phone Seed register
111 = Misc Control register
Writes to the selected shadow register are done
on a single cycle (no setup required).
Reads are selected by first writing to register 18h,
shadow 7, bits 14:12.
000
Bit Name RW Description Default
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