Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 327
Low Watermark Maximum Receive Frame Register (offset: 0x504)
APE_PERFECT_MATCH[1–4]_HIGH_REG (Offsets 0x540, 0x548,
0x550, 0x558)
There are total 4 Perfect (Destination Address) Match registers dedicated to APE in RX-MAC. These registers
hold the higher 2 octets of the matching address.
APE_PERFECT_MATCH[1–4]_LOW_REG (Offsets 0x544, 0x54C,
0x554, 0x55C)
There are total 4 Perfect (Destination Address) Match registers dedicated to APE in RX-MAC. These registers
hold the lower 4 octets of the matching address.
SGMII Control Register (offset: 0x5B0)
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
TXFIFO Almost Empty
Threshold
20:16 RW 0xC When the remaining entries of TXFIFO are less
than this threshold, TXFIFO_almost_empty will
be asserted. This value is used in conjunction
with Buffer Manager Mode register bit31 to
prevent EMAC TXFIFO underrun.
Low Watermark Max Receive
Frames
15:0 RW 0 Specifies the number of good frames to receive
after RX MBUF Low Watermark has been
reached. After the RX MAC receives this number
of frames, it will drop subsequent incoming
frames until the MBUF High Watermark is
reached.
Default to zero (i.e., drop frames ones RX MBUF
Low Watermark is reached).
Name Bits Access
Default
Value
Description
Reserved 31:29 RO 000 –
MAC High Address 15:0 RW 0x0000 Upper 2-bytes of APE's [1–4]th unicast address.
Name Bits Access
Default
Value
Description
MAC Low Address 31:0 RW 0x0000 Lower 4-bytes of APE's [1–4]th unicast address.
Name Bits Access
Default
Value
Description
Reserved – – – –