MSI-X PlumbingBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 244
MSI-X Plumbing
The basic interrupt/ISR model for NetXtreme controllers remains largely unchanged even with the introduction
of vectored interrupts in the form of MSI-X. However, there are four basic design changes:
• Replication of status blocks, mailboxes, etc. This essentially scales the legacy model from one vector to
five or 17 vectors.
• Implement MSI-X capability structures in PCIe configuration space.
• Implement PCI-mandated MSI-X data structures within each MAC core, including new base address
register (BAR) decoder, MSI-X table, pending bit array (PBA) structure, etc.
• Add per Rx queue host coalescing attributes.
Each item is discussed in detail in the following sections.
Replication of Status Blocks and INT Mailboxes
As shown in Table 91, all four Rx Return Consumer Indices are indicated in the legacy Status Block. When MSI-
X Multivector RSS mode is enabled, it leads to logically five interrupt vectors. Each of these vectors is bound to
its own status block; thus, there are five different status blocks, numbered Status-Block0 through Status-Block4.
Each of these five vectors is also bound to its own INT Mail-Box registers.
Each Status Block has a fixed location in the Host Memory. Hence, there are five Status Block Host Address
Registers (64-bit). Ta b le 91 shows all five Status-Block Host Address Registers and INT Mail-Box Registers.
Similarly, in case of MSI-X Multivector IOV mode, there are 17 sets of Status Blocks and MailBox registers.
Table 91: MIS-X Status-Block and Mail Box Addresses
Status
Block
Numbe
r
Status
Block Host
Address
Register
(64-bit)
IOV Mode RSS Mode
Comments
INT Mail
Box
Register
Address
Indication Items
INT Mail
Box
Register
Address
Indication Items
Legacy 0x3C3C,
0x3C38
0x200 (*) ALL 0x200(*) ALL Legacy Status Block.
Used by INTx or MSI.
Also used in MSI-X
Single-Vector RSS
mode or IOV mode
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