RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 447
Host Address for the DMA Read Channel 3 (offset: 0x4B40)
Non-LSO Read DMA Reserved Control Register (offset: 0x4B74)
Non-LSO Read DMA Flow Reserved Control Register (offset: 0x4B78)
Name Bits Access
Default
Value
Description
Host Addr 31:0 RO 0 Latched host address
Name Bits Access
Default
Value
Description
Txmbuf_margin 31:21 RO 0 –
Reserved 20 RO 0 –
FIFO High Mark 19:12 RO 0x90 –
FIFO Low Mark 11:4 RO 0x40 –
Slow Clock Fix Disable 3 RO 0 When cleared, it enables the fix to cover a corner
case in the link idle mode to allow the DMA Read
request to be generated when the core clock is
transitioning from slow to fast.
Hardware fix enable for DMA
FIFO Overrun
2 RO 0 When set, this bit enables the fix for DMA FIFO
overrun occurs if a large number of Rx BDs are
fetched while the Tx MBUF is full and the Read
DMA FIFO is empty.
Late Collision Fix Enable 1 RO 0 0: Disable Fix
1: Enable Fix
Select FED Enable 0 RO 0 Ensure only 1 request is generated upon any
condition where the core clock is switching from
slow to fast or vice-versa.
Name Bits Access
Default
Value
Description
Fix for frequent TX time out. 31:24 RW 0 This register contains various controls to
configure hardware fix for the chip getting stuck
in a permanent XOFF state under heavy
bi-directional netperf traffic when flow control is
enabled.
Fifo_threshold_mbuf_req 23:16 RO 0x30 –
MBUF Threshold MBUF
Request
15:8 RO 0x54 –
Reserved 7 RO 0 –
Clock Request Fix Enable 6 RO 0 –
MBUF Threshold Clk Req 5:0 RO 0x7 –
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