Broadcom NetXtreme/NetLink BCM5718 Series - Serdes PHY Register Definitions

SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 547
SerDes PHY Register Definitions
The PHY registers are broken into two blocks:
• Block 0 is for IEEE and non-IEEE controls.
• Blocks 0, 2 and 3 are non-IEEE blocks, where the analog section or the SerDes is controlled.
11 TEST MASTER/SLAVE
SEED
RW 1 = use MDIO programmable master/slave seed
0 = normal operation
0
10 WRITEABLE LINK
PARTNER ABILITY
RW 1 = link partner advertised ability may be
overwritten by MII management
0 = normal operation
0
9 FORCE HCD RW 1 = force auto-negotiation HCD resolution
(hcd can only be checked in register 19h bits
[10:8]; hcd status register will not be updated)
0 = normal operation
0
8 WRITEABLE LINK
PARTNER M/S SEED
RW 1 = link partner master/slave seed may be
overwritten by MII management
0 = normal operation
0
7 TRANSMIT 10B MODE RW 1 = force GMII transmit into 10B mode
0 = use normal mode bit
0
6 RECEIVE 10B MODE RW 1 = force GMII receive into 10B mode
0 = use normal mode bit
0
5 BYPASS TRANSMIT FIFO
modes:
(RGMII 10/100/1000
copper)
(SGMII 1000 towards
copper link partner)
(RGMII 100fx towards
SerDes link partner)
RW 1 = transmit FIFO bypassed
0 = normal operation
0
4 SAME SCRAMBLER
SEEDS
RW 1 = receive scrambler uses transmit seed
0 = normal operation
0
3 JITTER TEST MODE RW 1 = jitter test mode
0 = normal operation
0
2 TEST ATMP COUNTER RW 1 = force master slave seed attempt counter into
test mode
0 = normal mode
0
1 LATENCY MEASURE RW 1 = send special short packet to measure
receive latency on remote PHY (hold high)
0 = normal operation
0
0 DISABLE ACTIVE
HYBRID
RW 1 = active hybrid disabled
0 = active hybrid enabled
0
Bit Name RW Description Default