Miscellaneous Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 477
Miscellaneous Control Registers
Miscellaneous Control Register (offset: 0x6890)
Fast Boot Program Counter Register (offset: 0x6894)
Name Bits Access
Default
Value
Description
Reserved 31 RW 0 –
Cq14161_fix_ena_n 30 RW 0 This bit, when clear, enables the CQ14161 fix
where the proper Bus Number & Device Number
are returned in the completion prior to the initial
Configuration Write Request.
0: Enable Fix
1: Disable Fix
This bit is reset by Hard_Reset (POR, Exit Low
Power mode, Lost of Vmain while in D0)
Reserved 29:25 RW 0 –
MISC2 Bit 24 RW 0 Reserved RW bit that gets reset by Power-On-
Reset.
MISC 1 Bits 23:1 RW 0 Reserved RW bits that get reset by GRC Reset.
Reserved 0 RO 0 –
Name Bits Access
Default
Value
Description
Fastboot Enable 31 RW 0 This bit is used by the CPU to keep track of
whether or not there is valid phase 1 boot code
stored in the RX MBUF. If the bit is set, then
RXMBUF contains valid boot code. Otherwise, it
is assumed that RXMBUF does not contain valid
boot code. This bit is reset only by a power-on
reset. The state of this bit has no effect on state
machines within the device. It is used by the CPU
to track boot codestatus.
Fastboot Program Counter 30:0 RW 0 This field is used by the CPU to keep track of the
location of the phase 1 boot code in RX MBUF.
These bits behave identical to bit 31 in that they
have no effect on state machine operation and
they are cleared only by a power-on reset.
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