RX-CPU RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 451
RX-CPU Registers
All registers reset are core reset unless specified.
RX RISC Mode Register (offset: 0x5000)
Name Bits Access
Default
Value
Description
Reserved 31:15 RO 0 –
Enable register address trap
halt
14 RW 0 When set, if the GRC raises the trap signal to this
processor, it will halt. Cleared on reset and
Watchdog interrupt.
Enable memory address trap
halt
13 RW 0 When set, if the MA raises the trap signal to this
processor, it will halt. Cleared on reset and
Watchdog interrupt.
Enable Invalid Instruction
Fetch halt
12 RW 0 When set, the condition that causes RX RISC
state bit 6 to be set, also halts the RX RISC. Set
by reset.
Cleared by Watchdog interrupt.
Enable Invalid Data access
halt
11 RW 0 When set, the condition that causes RX RISC
state bit 5 to be set, also halts the RX RISC. Set
by reset.
Cleared by Watchdog interrupt.
Halt RX RISC 10 RW 0 Set by TX RISC or the host to halt the RX
RISC.Cleared on reset and Watchdog interrupt.
Flush Instruction Cache 9 WO 0 Self-clearing bit which forces the instruction
cache to flush.
Enable Instruction Cache
prefetch
8 RW 0 Enables prefetch logic within the instruction
cache. When disabled only a single cache line is
read on a cache miss. Cleared on reset.
Enable Watchdog 7 RW 0 Enables watchdog interrupt state machine. Used
in conjunction with Watchdog Clear register,
Watchdog Saved PC register and Watchdog
Vector register. Cleared on reset and Watchdog
interrupt.
ROM Fail 6 RW 1 Asserted on reset. Cleared by ROM code after it
successfully loads code from NVRAM.
Afterwards, this bit can be used by software for
any purpose.
Enable Data Cache 5 RW 0 Enables the data cache. Cleared on reset.
Note: Firmware developers should take care to
clear this bit before polling internal SRAM
memory locations, because the RX RISC
processor uses a two-element LRU caching
algorithm, which is not affected by writes from the
PCI interface.
To Next Page
Loading...
Need help?
General
