TCP Segmentation Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 347
TCP Segmentation Control Registers
All registers reset are core reset unless specified.
Lower Host Address Register for TCP Segmentation (offset: 0xCE0)
Upper Host Address Register for TCP Segmentation (offset: 0xCE4)
Length/Offset Register for TCP Segmentation (offset: 0xCE8)
Counter Value 9:0 RO 0 The current counter value for statistics kept by
the Send Data Initiator.
Name Bits Access
Default
Value
Description
Lower Host Address 31:0 RW 0 Specifies the lower 32bits of the starting address
in host memory where the transmit data buffer
resides.
Name Bits Access
Default
Value
Description
Upper Host Address 31:0 RW 0 Specifies the upper 32bits of the starting address
in host memory where the transmit data buffer
resides.
Name Bits Access
Default
Value
Description
Reserved 31:23 RO 0 –
MBUF Offset 22:16 RW 0 MBUF offset.
It specifies the offset of the first TXMBUF at
where DMA starts putting data. The valid value is
between 48 and 128.
Length 15:0 RW 0 Specifies the length of data to be transmitted.
Although firmware can specify up to 64 KB, it
should not attempt to program more than 8 KB
because it would exceed the size of TXMBUF.
Name Bits Access
Default
Value
Description
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