GRC RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 473
Timer Register (offset: 0x680C)
The Timer register is a 32-bit free-running counter. This counter increments when the Prescale Counter hits the
Timer Prescaler limit as specified by the Miscellaneous Configuration register. This counter is used by the CPU
to keep track of relative time in microseconds. A write to the Timer register will load the counter value written.
RX-CPU Event Register (offset: 0x6810)
Name Bits Access
Default
Value
Description
Timer Value 31:0 RW 0 32-bit free-running counter
Name Bits Access
Default
Value
Description
SW Event 13 31 RO 0 SW Event 13 is set; This bit is Flash Attention;
SW Event 12 30 RO 0 SW Event 12 is set; This bit is VPD Attention
Timer 29 RW 0 Timer Reference reached
SW Event 11 28 RW 0 SW Event 11 is set
Flow Attention 27 RO 0 Flow Attention
RX CPU Attention 26 RW 0 RX CPU needs attention.
MAC Attention 25 RO 0 MAC needs attention.
Reserved 24 RO 0 –
SW Event 10 23 RW 0 SW Event 10 is set.
High Priority Mailbox 22 RO 0 First 32 Mailbox registers have been updated.
Low Priority Mailbox 21 RO 0 Last 32 Mailbox registers have been updated.
DMA Attention 20 RO 0 A DMA channel needs attention.
SW Event 9 19 RW 0 SW Event 9 is set.
High DMA RD 18 RO 0 High Priority DMA read FTQ has stalled.
High DMA WR 17 RO 0 High Priority DMA write FTA has stalled.
SW Event 8 16 RW 0 SW Event 8 is set.
Host Coalescing 15 RO 0 The host coalescing FTQ has stalled.
SW Event 7 14 RW 0 SW Event 7 is set.
Receive Data Comp (Post
DMA)
13 RO 0 Receive data completion FTQ has stalled.
SW Event 6 12 RW 0 SW Event 6 is set.
RX SW Queue Event 11 RO 0 Receive Software Queue Event.
DMA RD 10 RO 0 Normal Priority DMA read FTQ has stalled.
DMA WR 9 RO 0 Normal Priority DMA write FTQ has stalled.
Read DMA Init (Pre DMA) 8 RO 0 Receive Data and Receive BD Initiator FTQ has
stalled.
SW Event 5 7 RW 0 SW Event 5 is set
Recv BD Comp 6 RO 0 Receive BD Completion FTQ has stalled.
SW Event 4 5 RW 0 SW Event 4 is set