GRC RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 472
Auto SEEPROM Access 24 RW 0 If set, access to serial EEPROM goes through
the serial EEPROM address and data registers.
Otherwise, serial EEPROM control register
should be used.
APE_GPIO IN(6:0) 23:17 RO APE GPIO
default
setting
APE GPIO Status
Holds the value of APE GPIO (6:0) pins
GPIO(2:0) Output 16:14 RW 0 Outputs which are defined by board level design.
GPIO(2:0) Output Enable 13:11 RW 0 When asserted, the device drives miscellaneous
pin outputs.
GPIO(2:0) Input 10:8 RO 0 Input from bidirectional miscellaneous pin.
GPIO(3) Output 7 RW 0 GPIO3 Output value.
GPIO(3) Output Enable 6 RW 0 When set to 1, GPIO3 pin will be enabled as an
output pin.
GPIO(3) Input 5 RW 0 Input value of GPIO3.
Reserved 4 RO 0 –
Interrupt on Attention 3 RW 0 If set, the host will be interrupted when any of the
attention bits in the CPU event register are
asserted.
Set Interrupt 2 WO 0 If Interrupt Mailbox 0 contains a nonzero value,
setting this bit does nothing. If Interrupt Mailbox
0 is zero, then setting this bit will cause the
internal unmasked interrupt state to be asserted.
The external interrupt state (INTA pin) will also be
asserted immediately if interrupts are not
masked by the Mask Interrupts bit. If interrupts
are masked, INTA will be asserted once
interrupts are unmasked, so long as interrupts
are not first cleared. This bit is not operational in
MSI mode.
Clear Interrupt 1 WO 0 This bit provides the same functionality as the
Clear Interrupt bit in the Miscellaneous Host
Control register. This bit is not operational in MSI
mode.
Interrupt State 0 RO 0 This bit reflects the state of the PCI INTA pin.
This bit is not operational in MSI mode.
Name Bits Access
Default
Value
Description
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