Transceiver RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 495
Section 14: Transceiver Registers
Purpose
This section describes the MII registers of the integrated 10/100/1000T PHY transceiver. The access to the
transceiver registers is provided indirectly through the MII Communication register (see “MII Communication
Register (offset: 0x44C)” on page 317) of the MAC. The integrated transceiver contains the set of registers
shown in the tables below.
BCM5718 Family MII Bus PHY Addressing
Table 119: BCM5717
Port 0 Port 1
Block PHY Address Block PHY Address
GPHY 0x01 GPHY 0x02
Table 120: BCM5718
Port 0 Port 1
Block PHY Address Block PHY Address
GPHY 0x01 GPHY 0x02
SERDES0x08 SERDES0x09
Table 121: BCM5719
Port 0 Port 1 Port 2 Port 3
Block
PHY
Address
Block
PHY
Address
Block
PHY
Address
Block
PHY
Address
GPHY 0x01 GPHY 0x02 GPHY 0x03 GPHY 0x04
SERDES 0x08 SERDES 0x09 SERDES 0x0A SERDES 0x0B
Table 122: BCM5720
Port 0 Port 1
Block PHY Address Block PHY Address
GPHY 0x01 GPHY 0x02
SERDES0x08 SERDES0x09
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