SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 548
To access block 0, 2 or 3, write to the block number into the Block Address register at address 0x1F (reserved
on each block).
Register Map
Table 125: GbE Port Internal PHY Register Map
Address Block Register Name Description
00h 0 MII CONTROL MII Control Register
01h 0 MII STATUS MII Status Register
02h 0 PHY ID MSB PHY_Identifier_MSB_Register
03h 0 PHY ID LSB PHY_Identifier_LSB_Register
04h 0 AUTONEGADV Auto-Negotiation advertisement register
05h 0 AUTONEG LINK PARTNER ABILITY Auto-Negotiation Link Partner Ability
06h 0 AUTONEGEXPANSION Auto-Negotiation Expansion register
07h–0Eh 0 – Reserved
0Fh 0 EXTENDEDSTATUS Extended Status register
10h 0 1000XCONTROL1 1000XControl 1 register
11h 0 1000XCONTROL2 1000XControl 2 register
12h 0 1000XCONTROL3 1000XControl 3 register
14h 0 1000XSTATUS1 1000XStatus 1 register
15h 0 1000XSTATUS2 1000XStatus 2 register
16h 0 1000XSTATUS3 1000XStatus 3 register
17h 0 – Reserved
18h 0 GE_PRBS_CONTROL Enable PRBS test mode
19h 0 GE_PRBS_STATUS PRBS test mode status
1Ah–1Eh 0 – Reserved
10h 2 FXCONTROL1 100FX Enabling Control register
11h 2 FXCONTROL2 100FX Extended Packet Size register
12h 2 FXCONTROL3 100FX Control register
13h 2 FXSTATUS1 100FX Link Status register
14h–1Eh 2 – Reserved
10h 3 ANALOG_TX1 Analog transmitter output for the SerDes when
it is in SGMII mode.
11h 3 ANALOG_TX2 Analog transmitter2 output for the SerDes when
it is in SGMII mode.
12h 3 ANALOG_TXAMP Analog transmitter output for the SerDes when
it is in FX (Fiber) mode.
13h 3 ANALOG_RX1 Controlling the SerDes receiver
14h 3 ANALOG_RX2 100FX Test Mode
18h 3 ANALOG_PLL Controlling the GE PLL circuitry
1Fh - BLOCKADDRESS Block address register
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