SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 558
1000XCONTROL3
Register Description: 1000X Control3 Register.
Register Offset: 0x12 at Block 0
Table 136: 1000XCONTROL3
Bits Name RW Description Default
15 DISABLE_PKT_ALIGNMENT RW 0 = Normal operation.
1 = Disable packet misalignment by carrier extend
and removing preamble.
0
14 RXFIFO_GMII_RST RW 0 = Normal operation.
1 = Reset receive FIFO and data_out_1000. FIFO
will remain in reset until this bit is cleared with a
software write.
0
13 DISABLE_TX_CRS RW 0 = Normal operation.
1 = Disable generating crs from transmitting in half-
duplex mode. Only receiving will generate crs.
1
12 INVERT_EXT_PHY_CRS RW 0 = Use “receive crs from PHY” pin.
1 = Invert “receive crs from PHY” pin
1
11 EXT_PHY_CRS_MODE RW 0 = Normal operation.
1 = Use external pin for the PHYs “receive only” crs
output. (Useful in SGMII 10/100 half-duplex
applications in order to reduce the collision domain
latency. Requires a PHY, which generates a
“receive only” crs output to a pin.)
1
10 JAM_FALSE_CARRIER_MO
DE
RW 0 = Normal operation.
1 = Change false carriers received into packets with
preamble only. (Not necessary if MAC uses crs to
determine collision)
0
9 BLOCK_TXEN_MODE RW 0 = Normal operation.
1 = Block txen when necessary to guarantee an ipg
of at least 6.5 bytes in 10/100 mode, 7 bytes in 1000
mode.
0
8 FORCE_TXFIFO_ON RW 0 = Normal operation.
1 = Force transmit FIFO to free-run in Gigabit mode
(Requires clk_in and pll_clk125 to be frequency
locked.)
0
7 BYPASS_TXFIFO1000 RW 0 = Normal operation.
1 = Bypass transmit FIFO in Gigabit mode. (Useful
for fiber or Gigabit only applications where the MAC
is using the pll_clk125 as the clk_in port. User must
meet timing to the pll_clk125 domain)
0
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