Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 393
Core Idle Detection De-Bounce Control Register (offset: 0x3648)
This register is reset by POR Reset or CPMU Register Software Reset.
Name Bits Access
Default
Value
Description
Link Idle Detection De-bounce
Timer
31:0 RW 0x20 De-bounce timer setting for core link from active
to non-active.
Unit is in number of CPMU clock cycles
Range: up to 232 CPMU clock cycles
Default Value (10 CPMU CLK) multiplied by
given Core CLK scale parameter below.
x1 00000: Core = 62.5 MHz (GPHY DLL/2)
x1 00001: Core = 60.0 MHz (Alt Source/2)
x2 00011: Core = 30.0 MHz (Alt Source/4)
x4 00101: Core = 15.0 MHz (Alt Source/8)
x8 00111: Core = 7.5 MHz (Alt Source/16)
x16 01001: Core = 3.75 MHz (Alt Source/32)
x8 10001: Core = 12.5 MHz (CK25/2)
x16 10011: Core = 6.25 MHz (CK25/4)
x32 10101: Core = 3.125 MHz (CK25/8)
x64 10111: Core = 1.563 MHz (CK25/16)
x128 11001: Core = 781 kHz (CK25/32),
x64 11111: Core = 12.5 MHz/1.25 MHz
(MII_CLK/2)
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