DMA ReadBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 57
DMA Read
Read Engine
The DMA read engine (see Figure 5) activates whenever a host read is initiated by the send or receive data
paths.
Figure 5: DMA Read Engine
The DMA read engine dequeues an internal data structure/request and performs the following functions:
• DMAs the data from the host memory to an internal Read DMA FIFO
• Moves the data from the Read DMA FIFO to NIC internal memory
• Classifies the frame
• Performs checksum calculations
• Copies the VLAN tag field from the DMA descriptor to the frame header
Read FIFO
The read FIFO provides elasticity during data movement from host memory to device local memory. The
memory arbiter is a gatekeeper for multiple internal blocks; several portions of the architecture may
simultaneously request internal memory. The PCI read FIFO provides a small buffer for the data read from host
memory while the Read DMA engine requests internal memory via the memory arbiter. The data is moved out
of the read DMA FIFO into device local memory once a memory data path is available. The FIFO isolates the
PCI clock domain from the device clock domain. This reduces latency internally and externally on the PCI bus.
The PCIe Read DMA FIFO holds 1024 bytes. The operation of the read DMA FIFO is transparent to host
software. The Read DMA engine makes sure there is enough space in internal Tx Packet Buffer Memory before
initiating a DMA request for transfer of Tx packet data from host memory to device internal packet memory.
text
text
DMA
BD Packet#1
Host Send Buffer
Descriptors
Packet Data #1
Host Send Buffer
Memory
Buffer Manager
BD Packet#1
Frame Classify &
Checksum
Calculation
text
Packet Data #1
Frame Header #1
NIC BD
Memory
NIC Buffer
Memory
Tx
FIFO
Frame
Mod
TX
MAC
Statistics
TX
PCS
TX
RMII
TX
GMII
TX
IO
6416
Read
FIFO
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