Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Receive Data and Receive BD Initiator Control RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 365
VRQ Flush Timer Register (offset: 0x2414)
RDI B2HRX Hardware Debugging Register (offset: 0x2418)
Jumbo Producer Ring Host Address High Register (offset: 0x2440)
VRQ hardware Flush enable 0 RW 0x0 This value will be loaded into a count-down
counter triggered by a falling-edge of any bit of
VRQ Enable register (0x560). The count-down is
based on internal CORE_CLK. The purpose of
this counter is to allow hardware to drain out
certain pending DMA requests within WDMA
pipeline and PCIE core. Once the timer expires,
hardware shall invoke the Automatic VRQ Flush
Procedure. A value 0x0 in this register effectively
zeroes this timer count.
Name Bits Access
Default
Value
Description
IOV Flush Timer 31:0 RW 0x0 This value will be loaded into a count-down
counter triggered by a falling-edge of any bit of
VRQ Enable register (0x560). The count-down is
based on internal CORE_CLK. The purpose of
this counter is to allow hardware to drain out
certain pending DMA requests within WDMA
pipeline and PCIE core. Once the timer expires,
hardware shall invoke the Automatic VRQ Flush
Procedure. A value 0x0 in this register effectively
zeroes this timer count.
Name Bits Access
Default
Value
Description
Legacy 31:0 RO 0x0 RDI internal B2HRX status.
Name Bits Access
Default
Value
Description
Host Address High 31:0 RW 0 The host ring address is the host address of the
first ring element.
The host ring address is in host address format.
Name Bits Access
Default
Value
Description

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General

Brand	Broadcom
Model	NetXtreme/NetLink BCM5718 Series
Category	Controller
Language	English