Non-Volatile Memory (NVM) Interface RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 488
NVM Write Register (offset: 0x7008)
NVM Address Register (offset: 0x700C)
NVM Read Register (offset: 0x7010)
Wr 5 RW 0 The write/not read command bit.
Set to execute write or erase.
Doit 4 RW 0 Command from software to start the defined
command. The done bit must be clear before
setting this bit. This bit is self clearing and will
remain set while the command is active.
Done 3 WTC 0 Sequence completion bit that is asserted when
the command requested by assertion of the doit
bit has completed.
The done bit will be cleared while the command
is in progress. The done bit will stay asserted
until doit is reasserted or the done bit is cleared
by writing a 1 to the done bit. The done bit is the
FLSH_ATTN signal.
Reserved 2:1 RO 0 –
Reset 0 RW When set, the entire NVM state machine is reset.
This bit is self clearing.
Name Bits Access
Default
Value
Description
Write Data 31:0 RW 0 32bits of write data are used when write
commands are executed.
Name Bits Access
Default
Value
Description
Reserved 31:24 RO 0 –
Address 23:0 RW 0 The 24 bit address for a read or write operation
(must be 4 byte aligned).
Name Bits Access
Default
Value
Description
Read Data 31:0 RO 0 32bits of read data are used when read
commands are executed.
Name Bits Access
Default
Value
Description