Endian Control (Byte and Word Swapping)BCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 195
As illustrated above, because the Ethernet controller uses an internal 64-bit big endian architecture, it will map
(by default) the most significant byte of an 8-byte (64-bit) internal quantity to the most significant byte on a 64-
bit PCI bus. This works nicely for quantities (fields) that are 64 bits in size (e.g., a host physical address).
However, this can be confusing for quantities that are 32 bits in size. Without Word Swapping enabled, the host
could easily access the wrong 32-bit quantity when making a 32-bit access.
Take, for example, a Ring Control Block (RCB). RCBs are on-chip structures and read/written by the host via
PCI target accesses. The table below shows the big-endian layout of an on-chip RCB:
If Word Swapping is not enabled, and the host made a 32-bit read request to address 0x08, the four bytes of
data returned on the PCI bus would actually be the NIC Ring Address rather than the Max_Len and Flags fields.
This initially might seem counter-intuitive, but is explained in Ta bl e 57 . Therefore, if a software driver running on
an x86 host (Little Endian) referenced on-chip data structures as they are defined in the Ethernet controller data
sheet, the driver should set the Enable Endian Word Swap bit. By setting this bit, the translation would be as
follows:
Example Content 88 89 8A 8B 8C 8D 8E 8F
MSB LSB
PCI Byte # 76543210
PCI Bit #63473115
Example Content 88 89 8A 8B 8C 8D 8E 8F
Table 55: Default Translation (No Swapping) on 32-bit PCI
31 16 15 0 31 16 15 0
0x00 88 89 8A 8B 8C 8D 8E 8F 0x00
0x04 8C 8D 8E 8F 88 89 8A 8B 0x04
Table 56: RCB (Big Endian 32-Bit Format)
Byte #0 123
Bit # 31 15
MSB Host Ring Address 0x00
0x04
MSB MAX_Len Flags 0x08
NIC Ring Address 0x0C
Table 57: Internal Byte OrderingPCI Byte Ordering
31 16 15 0 31 16 15 0
0x00 88 89 8A 8B 88 89 8A 8B 0x00
Table 54: Default Translation (No Swapping) on 64-Bit PCI (Cont.)
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