Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 328
SGMII Status Register (offset: 0x5B4)
This register reflects various status of the respective SGMII port when enabled.
HTX2B Perfect Match[1–4] HI Reg (offset: 0x4880, 0x4888, 0x4890,
0x4898)
There are four Perfect (Destination Address) Match registers in DMAR for HTX2B. These registers hold the
higher two octets of the matching address.
HTX2B Perfect Match[1–4] LO Reg (offset: 0x4884, 0x488C, 0x4894,
0x489C)
There are four Perfect (Destination Address) Match registers in DMAR for HTX2B. These registers hold the
lower two octets of the matching address.
Name Bits Access
Default
Value
Description
LP AutoNeg Capability 31:16 RO 0 Link partner advertised auto-negotiation abilities.
Reserved 15:11 RO 0 –
External CRS Detect 10 RO 0 External PHY's CRS output
PCS CRS Detect 9 RO 0 Internal PCS blocks CRS output
Media Selection mode 8 RO 0 1: SGMII/1000BaseX mode selected for this port
0: Copper Media Selected for this port
Pause TX 7 RO 0 1: enable pause TX
Pause RX 6 RO 0 1: enable pause RX
AutoNeg Next Page RX 5 RO 0 1: next auto-negotiation page received
Speed_100 4 RO 0 The SGMII Link currently operable at 100mbps
data speed.
Speed_1000 3 RO 0 The SGMII Link currently operable at 1 Gbps
data speed.
Duplex Status 2 RO 0 1: The Link currently is in Full Duplex mode.
0: The Link is currently in Half Duplex mode.
Link Status 1 RO 0 1: Link is up.
0: Link is down.
AutoNeg Completion 0 RO 0 Auto-negotiation process has completed.
Name Bits Access
Default
Value
Description
Reserved 31:29 RO 000 Reserved.
MAC High Address 15:0 RW 0x0000 Upper 2-bytes Destination Address.
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