Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 404
Link Idle Status Register (offset: 0x3674)
This register is reset by POR Reset or CPMU Register Software Reset.
Name Bits Access
Default
Value
Description
Reserved 31:25 DC — Readable and writeable reserved bits
PCIE Idle 24 RO — Idle Status.
1: Idle
0: Busy
APE ATP Empty 23 RO —
APE ATPM Idle 22 RO —
DBU Idle 21 RO —
NVM Idle 20 RO —
SBDI Idle 19 RO —
RBDI Idle 18 RO —
MB Idle 17 RO —
Reserved 16 DC — –
WDMA Idle 15 RO — Idle Status.
1: Idle
0: Busy
RDMA Idle 14 RO —
MSI Idle 13 RO —
TXMAC FIFO empty 12 RO —
RXMAC FIFO empty 11 RO —
COL = 0 10 RO —
CRS = 0 9 RO —
TXAMAC Idle 8 RO —
RXER = 0 7 RO —
RXDV = 0 6 RO —
MDIO Idle 5 RO —
FTQ empty 4 RO —
GRC Idle 3 RO —
MBUF empty 2 RO —
MA Idle 1 RO —
No core reset 0 RO —