Non-Volatile Memory (NVM) Interface RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 489
NVM Config 1 Register (offset: 0x7014)
Name Bits Access Default Value Description
SEE_CLK_DIV
Enable
31 0 RW This bit enables 0x7014[21:11] as the
SEE_CLK_DIV count for EPROM clock
generation.
1 = Enable
0 = Disable
Page Size 30:28 Depend
s on
flash
strappin
g
RW These bits indicate the page size of the attached
flash device. They are set automatically
depending on the chosen flash as indicated by
the strapping option pins.
Page sizes are as follows:
000b: 256 bytes
001b: 512 bytes
010b: 1024 bytes
011b: 2048 bytes
100b: 4096 bytes
101b: 264 bytes
110b: reserved
111b: reserved
Reserved 27 RO –
Reserved–Safe Erase 26 RO 0 –
Flash Size–strap bit 3 25 RO Pin –
Protect Mode–strap bit
2
24 RO pin –
Strap bit 5 23 RO pin –
Strap bit 4 22 RO pin –
SEE_CLK_DIV 21:11 RW 16 This field is a divisor used to create all 1x times
for all SEEPROM interface I/O pin timing
definitions. A value of 0 means that an SCL
transitions at a minimum of each CORE_CLK
rising edge.
The equation to calculate the clock freq. for SCL
is:
CORE_CLK / ((SEE_CLK_DIV + 1) * 4)
SPI_CLK_DIV 10:7 RW 4 This field is a divisor used to create all 1x times
for all Flash interface I/O pin timing definitions. A
divisor of 0 means that an SCK transitions at a
minimum of each CORE_CLK rising edge.
The equation to calculate the clock freq. for SCK
is:
CORE_CLK / ((SPI_CLK_DIV + 1) * 2)
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