Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 318
MII Status Register (offset: 0x450)
MII Mode Register (offset: 0x454)
Transaction Data 15:0 RW 0 When configured for a write command, the data
stored at this location is written to the PHY at the
specified PHY and register address.
During a read command, the data returned by the
PHY is stored at this location.
Name Bits Access
Default
Value
Description
Reserved 31:2 RO 0 –
Mode 10 Mbps 1 RW 0 When read, a value of 1 indicates the transceiver
device is operating in 10 Mbps mode
Link Status 0 RW 0 The bit will generate an attention if enabled.
Indicates status of the link on the transceiver
device.
When read, a value of 1 indicates the transceiver
is linked
Name Bits Access
Default
Value
Description
Reserved 31:21 RO 0 –
MII Clock Count 20:16 RW 0Ch Counter to divide CORE_CLK (62.5 MHz) to
generate the MI clock.
The formula is:
MI Clock = CORE_CLK/2/(MI Clock Count + 1).
Constant MDIO/MDC clock
speed.
15 RW 0 Enable ~500Khz constant MII management
interface (MDIO/MDC) frequency regardless
core clock frequency.
1: Enable
0: Disable
Reserved 14:10 RO 0 –
PHY Address 9:5 RW 1 This field specifies the PHY Address.
Port polling 4 RW 0 Set to enable autopolling of the transceiver link
information from the MII management interface.
If cleared, the device will obtain the link status
information from the state of the LINKRDY input
signal.
Reserved 3 RO 0 –
Auto_control 2 RW 0 –
Use Short Preamble 1 RW 1 Use short preamble while polling, if set.
Name Bits Access
Default
Value
Description
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