RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 446
Non-LSO Read DMA Programmable IPv6 Extension Header Register
(offset: 0x4B08)
Host Address for the DMA Read Channel 0 (Offset: 0x4B28)
Host Address for the DMA Read Channel 1 (offset: 0x4B30)
Host Address for the DMA Read Channel 2 (offset: 0x4B38)
Name Bits Access
Default
Value
Description
Programmable Extension
Header Type #2 Enable
31 RO 0 This bit enables programmable extension header
#1. If this bit is clear, then the value programmed
in bits [15:8] of this register will be ignored. If this
bit is set, then extension headers will be checked
for a type matching the value in bits [15:8].
Programmable Extension
Header Type #1 Enable
30 RO 0 This bit enables programmable extension header
#1. If this bit is clear, then the value programmed
in bits [7:0] of this register will be ignored. If this
bit is set, then extension headers will be checked
for a type matching the value in bits [7:0].
Reserved 29:28 RO 0 –
ch0_rlctr 27:19 RO 0 –
Reserved 18:16 RO 0 –
Programmable Extension
Header Type #2
15:8 RO 0 These bits contain the programmable extension
header value for programmable header #2.
Programmable Extension
Header Type #1
7:0 RO 0 These bits contain the programmable extension
header value for programmable header #1.
Name Bits Access
Default
Value
Description
Host Addr 31:0 RO 0 Latched host address
Name Bits Access
Default
Value
Description
Host Addr 31:0 RO 0 Latched host address
Name Bits Access
Default
Value
Description
Host Addr 31:0 RO 0 Latched host address