Configuration SpaceBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 171
• MAC local memory
Functional Overview
PCI Configuration Space Registers
The Ethernet controller configuration space can be broken into two regions: Header and Device Specific.
Table 47 on page 172 shows the registers implemented to support PCI/PCI-X/PCIe functionality in the Ethernet
controller. Reserved fields in PCI configuration registers will always return zero.
PCI Required Header Region
The bit-7 of the Header Type register (Offset 0x0E) in the PCI Required Header Region is used to identify
whether the device is a single function device or multifunction device.
Figure 33: Header Type Register 0xE
Single function PCI devices may decode access to non-implemented device functions in two ways, per Section
3.2.2.3.4 of the PCI 2.2 specification:
• A single function device may optionally respond to all function numbers as the same.
• May decode the function number field and respond only to function 0.
The Ethernet controller single function chips follow the stated technique #1— BIOS code scanning
multifunctions get a target response from function(s) 1–7, but these functions are essentially shadows of
function 0. Software that programs to function(s) 1–7 is remapped to function 0.
Note: BIOS programmers should take special care to read bit_7 in PCI Header Type register (Offset
0x0E) before scanning the Ethernet controller PCI configuration space.
Func
DeviceFunctions:
Single Function = 0
Multi-Function = 1
Header Layout
[0]
[6][7]
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