Receive List Placement RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 358
Receive Selector Non-Empty Bits Register (offset: 0x200C)
This 32-bit register is used by the RISCs to quickly determine the status of the receive selector. Bit 0 refers to
receive selector list 1. Bit 15 refers to receive selector list 16. If this register is nonzero the receive selector non-
empty bit is set in the RXCPU event register.
Receive List Placement Configuration Register (offset: 0x2010)
Name Bits Access
Default
Value
Description
Reserved 31:16 RO 0 –
List non-empty bits 15:0 RO – If set, the bit indicates that the associated list is
not empty (that is the counter is nonzero).
Name Bits Access
Default
Value
Description
Reserved 31:15 RO 0 –
Default Interrupt Distribution
Queue
14:13 RW 0 Default interrupt distribution queue. Number
within a class of service group when the frame
has errors, is truncated, or is a non-IP frame.
Bad Frames Class 12:8 RO 1 Default class for error or truncated frames. These
frames are placed in this class of service group
when the Allow Bad Frame bit (bit 11) is set in the
Mode Control Register.
Number of Active Lists 7:3 RW 0 The total number of active receive lists. The
value must be between 1 and 16. This value
must be an integer multiple of the Number of
Lists per Distribution Group value.
Number of Lists per
Distribution Group
2:0 RW 0 Specifies the number of lists per interrupt
distribution group. This register must always be a
power of 2. For example, if the system wants four
classes of service and four interrupt distribution
lists per class of service, this value is set to four
and the Number of Active Lists value is set to 16.
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