RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 436
LSO Read DMA Reserved Control Register (offset: 0x4900)
LSO Read DMA Flow Reserved Control Register (offset: 0x4904)
Programmable Extension
Header Type #1
7:0 RW 0 These bits contain the programmable extension
header value for programmable header #1.
Name Bits Access
Default
Value
Description
FIX for controller stop passing
traffic
31:21 RW 0 Fix the controller stop passing traffic when flow
control is enabled. It appears that the chip can
get stuck in a permanent XOFF state under
heavy bi-directional netperf traffic when flow
control is enabled.
Fix in A1 for Rx discard counter
update in offset x2250 when
multicast/unicast/broadcast
packets are dropped
20 RW 0 0: Enable fix
1: Disable fix
FIFO High Mark 19:12 RW 0x90 –
FIFO Low Mark 11:4 RW 0x40 –
Slow Clock Fix Disable 3 RW 0 When cleared, it enables the fix to cover a corner
case in the link idle mode to allow the DMA Read
request to be generated when the core clock is
transitioning from slow to fast Enable hardware
fix 25155.
Fix for the DMA FIFO overrun 2 RW 0 When set, this bit enables the fix, where a DMA
FIFO overrun occurs if a large number of Rx BDs
are fetched while the Tx MBUF is full and the
Read DMA FIFO is empty.
Late Collision Fix Enable 1 RW 0 0: Disable Fix
1: Enable Fix
Select FED Enable 0 RW 0 Ensure only 1 request is generated upon any
condition where the core clock is switching from
slow to fast or vice-versa.
Name Bits Access
Default
Value
Description
Fix for frequent TX time out. 31:24 RW 0 This register contains various controls to
configure hardware fix for the chip getting stuck
in a permanent XOFF state under heavy
bi-directional netperf traffic when flow control is
enabled.
Fifo_threshold_mbuf_req 23:16 RW 0x30 –
MBUF Threshold MBUF
Request
15:8 RW 0x54 –
Name Bits Access
Default
Value
Description
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