GRC RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 470
Miscellaneous Configuration Register (offset: 0x6804)
No Frame Cracking 9 RW 0 Turn off all frame cracking functionality in both
the read DMA engine and the MAC receive
engine. On receive, the TCP/UDP checksum
field is replaced by raw checksum for the whole
frame except the Ethernet header.
On transmit, IP and TCP/UDP checksum
generation is always disabled when this bit is set.
Also, the raw checksum is calculated over the
entire frame except the Ethernet header and
CRC.
IOV Mode Enable 8 RW 0 When this bit is written 1, the chip enters IOV-
MODE.
When this bit is written 0, the chip operates in
legacy mode.
This bit must only be configured during boot-up
and must not be changed afterwards.
Legacy 7:0 Defined by Legacy
Byte Swap for B2HRX Data 7 RW 0 This bit must be 1 for proper B2HRX operation in
case of Little-Endian Host machines.
Word Swap for B2HRX Data 6 RW 0 This bit must be 1 for proper B2HRX operation in
case of Little-Endian Host machines.
Word Swap Data 5 Host-
RW NIC-
R
0 Word swap data when DMAing it across the
PCIE bus.
Byte Swap Data 4 Host-
RW NIC-
R
0 Byte swap data when DMAing it across the PCIE
bus.
FLR state 3 RO 0 When this bit is set, it means PCIE is in FLR state
for this MAC core.
Word Swap BD 2 Host-
RW NIC-
R
0 Word swap BD structure when DMAing them
across the PCIE bus.
Byte Swap BD 1 Host-
RW NIC-
R
0 Byte swap BD structure when DMAing them
across the PCIE bus.
Reserved 0 RO 0 –
Name Bits Access
Default
Value
Description
ID7 31 RO ID7 Bond ID 7
ID6 30 RO ID6 Bond ID 6
Disable GRC Reset on PCIE
block
29 RW 0 Setting this bit will prevent reset to PCIE block.
ID5 28 RO ID5 Bond ID 5
Name Bits Access
Default
Value
Description
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