Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 317
Gigabit PCS Test Register (offset: 0x440)
Transmit 1000BASE-X Auto-Negotiation Register (offset: 0x444)
Receive 1000BASE-X Auto-Negotiation Register (offset: 0x448)
MII Communication Register (offset: 0x44C)
Name Bits Access
Default
Value
Description
Reserved 31:0 RO 0 –
Name Bits Access
Default
Value
Description
Reserved 31:0 RO 0 –
Name Bits Access
Default
Value
Description
Reserved 31:0 RO 0 –
Name Bits Access
Default
Value
Description
Reserved 31:30 RO 0 –
Start/Busy 29 RW 0 Set this bit to start a transaction.
While it is high, it indicates that the current
transaction is still ongoing.
If enabled, generates an attention via EMAC
Status Register MI Completion bit (bit 22).
Read Failed 28 RO 0 When set, the transceiver device did not driver
the bus during the attempted read transaction.
Valid after the Start/Busy bit is cleared.
Command 27:26 RW 0 These bits specify the transaction type:
11: Undefined
10: Read command
01: Write command
00: Undefined
PHY Addr 25:21 RW 0 0x8: SGMII SerDes Port0.
0x9: SGMII SerDes Port1.
as strapped: External PHY Port0
as strapped: External PHY Port1
Register Address 20:16 RW 0 Address of the register to be read or written.