Device Closing ProcedureBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 147
a. Set the Enable_Endian_Word_Swap bit in the Miscellaneous Host Control register, when the host
processor architecture is little-endian. Set the Enable_Endian_Word_Swap bit and the
Enable_Endian_Byte_Swap bit in the Miscellaneous Host Control register, when the host processor
architecture is big-endian.
b. Enable the indirect register pairs by setting the Enable_Indirect_Access bit in the Miscellaneous Host
Control register (see “Indirect Mode” on page 172).
c. Enable the PCI State register to allow the device driver read/write access by setting the
Enable_PCI_State_Register bit in the Miscellaneous Host Control register.
10. Set Word_Swap_Data, Byte_Swap_Data, and win the General Mode Control register when the host
processor architecture is little endian. Optionally, set Byte_Swap_Non_Frame_Data in the General Mode
Control register when the host processor architecture is big endian, (see “Mode Control Register (offset:
0x6800)” on page 468).
11. Poll for bootcode completion. The device driver must poll the general communication memory at 0xB50 for
the one is complement of the T3_MAGIC_NUMBER (that is, 0xB49A89AB). The bootcode should complete
initialization within 1000 ms for Flash devices and 10000 ms for SEEPROM devices.
Device Closing Procedure
This section describes the device close procedure for the MAC portion of the NetXtreme family of devices.
1. Disable Host Interrupt.
a. Set the Mask_Interrupt bit in the Miscellaneous Host Control register (offset: 0x68) to disable interrupt
b. Set the interrupt mail box register (offset: 0x200)
2. Tell Firmware the driver are shutting down and doing prereset.
Note: Do this only if ASF enabled.
a. Write the 0x2 to the device memory (offset: 0xB78) to PAUSE the firmware
b. Set the RX-CPU Event register (offset: 0x6810) bit14 (SW Event 7) 7 bit and wait for SW bit14 (SW Event
7) to be clear
c. Write MAGIC Number 0x4B657654 to the device memory (offset: 0xB50)
d. Write 0x2 to the device memory (offset 0xc04)
3. Disable all the receiver blocks.
a. Clear the Enable bit in the Receive MAC Mode register (offset: 0x468)
b. Clear the Enable bit in the Receive BD Initiator Mode register (offset: 0x2C00)
c. Clear the Enable bit in the Receive List Placement Mode register (offset: 0x2000)
d. Clear the Enable bit in the Receive BD Initiator Mode register (offset: 0x2400)
e. Clear the Enable bit in the Receive Data Completion Mode Register (offset: 0x2800)
f. Clear the Enable bit in the Receive BD Completion Mode Register (offset: 0x3000)
4. Disable all the transmit blocks.
a. Clear the Enable bit in the Send BD Selector Mode register (offset: 0x1400)
b. Clear the Enable bit in the Send BD Initiator Mode Register (offset: 0x1800)
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