Broadcom NetXtreme/NetLink BCM5718 Series - TX TIME STAMP MSB REG [Offset 0 X05 C4]; RX TIME STAMP LSB REG [Offset 0 X06 B0]; RX TIME STAMP MSB REG [Offset 0 X06 B4]; RX PTP SEQUENCE ID REG [Offset 0 X06 B8]

Time Sync RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 163
TX TIME STAMP MSB REG [Offset 0X05C4]
RX TIME STAMP LSB REG [Offset 0X06B0]
RX TIME STAMP MSB REG [Offset 0x06B4]
This MSB and LSB pair captures the time-stamp (63-bits) of received PTP packets when qualified to do so. HW
overwrite of the Time Stamp value is controlled by an interlock policy – See “RX PTP CONTROL REG [Offset
0X06C8]” on page 164. The MSB and LSB registers may be accessed in the order of LSB first and MSB second
– else the Valid / Interlock bit would not serve its purpose.
RX PTP SEQUENCE ID REG [Offset 0X06B8]
Name Bits Access Default Value Description
TX Time Stamp [lower
half]
31:0 RO U LSB of the TX Time Stamp – Reading this LSB
freezes the time stamp and is only unfrozen when
the corresponding MSB is read.
Name Bits Access Default Value Description
TX Time Stamp [Upper
half]
31:0 RO U MSB of the TX Time Stamp – Reading this MSB
unfreezes the time stamp which was earlier frozen by
the corresponding LSB read.
Name Bits Access Default Value Description
RX Time Stamp [lower
half]
31:0 RO U LSB of the RX Time Stamp.
Name Bits Access Default Value Description
RX Time Stamp Valid /
Interlock
31 RO U This bit is set by hardware in conjunction with posting
a new value in the Time Stamp MSB and LSB fields.
When this bit is 1 and SW executes a read to the RX
TIME STAMP MSB Register, hardware shall clear
this bit – the reset behavior of this bit is influenced by
RX PTP CONTROL Register’s [RX TIME STAMP
INTERLOCK POLICY] field.
RX Time Stamp [Upper
half]
30:0 RO U MSB of the RX Time Stamp.
Name Bits Access Default Value Description
Reserved 31:16 RO 0x0000