Power ManagementBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 191
GPIO
The use of GPIO pins for power management is design-specific, though Broadcom-delivered drivers use GPIO
pins in the manner listed in Ta b le 49 . This usage is only applicable when the Ethernet controller is configured
for a NIC design; it is not applicable to LAN-on-Motherboard (LOM) designs.
Power Supply in D3 State
Ta b le 5 0 shows the power supply to various power pins on the Ethernet controller, and it is assumed that host
software has switched power regulators using GPIO pins 0, 1, and 2.
Clock Control
Certain functional blocks in the MAC architecture should be powered down before a transition to D3 ACPI state.
MAC clock generators/PLLs drive transistor level logic, which switch states on every clock pulse. Transistor level
switching consumes power (mW). Software should selectively disable clocking to non-essential functional
blocks. Software must set the Enable_Clock_Control_Register bit in the Miscellaneous Host Control register
(see “Miscellaneous Host Control Register (offset: 0x68)” on page 282); the assertion of this bit allows host
software to configure the PCI clock control register. The following clock bits should be configured in the PCI
Clock Control register:
• RX RISC clock disable
• Select alternate clock—the 133 MHz PLL is not used as reference clock.
Table 49: GPIO Usage for Power Management for Broadcom Drivers
a
a. x= Don’t Care
Function Description GPIO0 GPIO1 GPIO2
VAux Sequence for switching to VAux 0 1 1
111
110
VMain Sequence for switching to VMain x 1 x
x0x
x1x
Table 50: Ethernet Controller Power Pins
Supply Pins D0 Normal D3 Hot, D3 Cold
VDDIO PCIe Slot Vmain PCIe Slot Vaux
VDDC PCIe Slot Vmain PCIe Slot Vaux
Note: For the 57818 family chip, the clock control register (offset: 0x68) does not need to be
configured.
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