SerDes PHY Register DefinitionsBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 569
ANALOG_RX2
Register Description: 100FX Test Mode
Register Offset: 0x14 at Block 3
ANALOG_PLL
Register Description: Controlling the GE PLL circuitry.
Register Offset: 0x18 at Block 3
Table 148: ANALOG_RX2
Bits Name RW Description
Defaul
t
15:4 RESERVED RW Reserved 0x000
3 100FX_ENABLE RW Set to enable SerDes in 100-FX mode.
1 = FX100 mode
0 = Normal operation
0
2:0 RESERVED RW Reserved 0x0
Table 149: ANALOG_PLL
Bits Name RW Description Default
15:1 RESERVED RW Reserved 0x4040
0 PLL_POWER_DOWN RW 1 = PLL power down
0 = Normal operation
0
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