Receive List Placement RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 360
Receive List Placement Statistics Increment Mask Register (offset:
0x201C)
Receive Selector List Head & Tail Pointers (offset: 0x2100)
The 16 receive selector lists head and tail pointers are MBUF cluster pointers. The selector list head pointer is
the MBUF cluster pointer of the first frame queued in the associated selector list. Similarly, the selector list tail
pointer is the MBUF cluster pointer of the last frame queued in that selector list.
Receive Selector List 1 Count Registers (Offset: 0x2108)
These registers indicate how many frames are currently queued to the associated selector list.
Receive Selector List 2 Count Register (offset: 0x2118)
Receive Selector List 3 Count Registers (offset: 0x2128)
Receive Selector List 4 Count Registers (offset: 0x2138)
Receive Selector List 5 Count Registers (offset: 0x2148)
Receive Selector List 6 Count Registers (offset: 0x2158)
Receive Selector List 7 Count Registers (offset: 0x2168)
Receive Selector List 8 Count Registers (offset: 0x2178)
Reserved 0 RO 0 –
Name Bits Access
Default
Value
Description
Reserved 31:22 RO 0 –
Counters Increment Mask 21:16 WO 0 Writing a 1 to a Counters Increment Mask bit
forces the corresponding statistics counter to
increment by 1. Not affected by Statistics Enable
Mask.
Bits 16-21 correspond to statistics for Drop due
to filter, DMA Write Queue Full, DMA High
Priority Write Queue Full, No More Receive BD,
ifInDiscards, and ifInErrors.
Reserved 15:1 RO 0 –
Counters Increment Mask 0 WO 0 Writing a 1 to a Counters Increment Mask bit
forces the corresponding statistics counter to
increment by 1. Not affected by Statistics Enable
Mask.
Bit 0 corresponds to statistics Class of Service 1.
Name Bits Access
Default
Value
Description
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