Flow Through QueuesBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 464
FTQ Reset Register (offset: 0x5C00)
Name Bits Access
Default
Value
Description
Reserved 31:17 RO 0 –
Reset Receive Data
Completion FTQ
16 RW 0 Set this bit to reset the Receive Data Completion
flow through queue.
When set to 0, this FTQ is ready for use.
This bit is self-clearing.
Reserved 15 RO 0 –
Reset Receive List Placement
FTQ
14 RW 0 Set this bit to reset the Receive List. This bit self-
clearing placement flow through queue.
When set to 0, this FTQ is ready for use. This bit
is self-clearing
Reset Receive BD Complete
FTQ
13 RW 0 Set this bit to reset the Receive BD Complete
flow through queue.
When set to 0, this FTQ is ready for use.
This bit is self-clearing
Reserved 12 RO 0 –
Reset MAC TX FTQ 11 RW 0 Set this bit to reset the MAC TX flow through
queue. When set to 0, this flow through queue is
ready for use.
This bit is self-clearing.
Reset Host Coalescing FTQ 10 RW 0 Set this bit to reset the Host Coalescing flow
through queue. When set to 0, this flow through
queue is ready for use. This bit is self-clearing.
Reset Send Data Completion
FTQ
9 RW 0 Set this bit to reset the Send Data Completion
flow through queue. When set to 0, this flow
through queue is ready for use. This bit is self-
clearing.
Reserved 8 RO 0 –
Reset DMA High Priority Write
FTQ
7 RW 0 Set this bit to reset the DMA High Priority Write
flow through queue. When set to 0, this flow
through queue is ready for use. This bit is self-
clearing.
Reset DMA Write FTQ 6 RW 0 Set this bit to reset the DMA Write flow through
queue. When set to 0, this flow through queue is
ready for use.
This bit is self-clearing.
Reserved 5 RO 0 –
Reset Send BD Completion
FTQ
4 RW 0 Set this bit to reset the Send BD Completion flow
through queue. When set to 0, this flow through
queue is ready for use. This bit is self-clearing.
Reserved 3 RO 0 –
Reset DMA High Priority Read
FTQ
2 RW 0 Set this bit to reset the DMA High Priority Read
flow through queue. When set to 0, this flow
through queue is ready for use. This bit is self-
clearing.
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