Initialization ProcedureBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 145
55. Set 0x4910[19:18] = 11b to allow 4KB burst length reads for non-LSO (i.e. standard) network frames.
56. Enable the receive data completion functional block by setting the Enable and Attn_Enable bits in the
Receive Data Completion Mode register (see “Receive Data Completion Mode Register (offset: 0x2800)” on
page 371).
57. Enable the send data completion functional block by setting the Enable bit in the Send Data Completion
Mode register (see “Send Data Completion Mode Register (offset: 0x1000)” on page 350).
58. Enable the send BD completion functional block by setting the Enable and Attn_Enable bits in the Send BD
Completion Mode register (see “Send BD Completion Control Registers” on page 356).
59. Enable the receive data and BD initiator functional block by setting the Enable and Illegal_Return_Ring_Size
bits in the Receive Data and Receive BD Initiator Mode register (see “Receive Data and Receive BD Initiator
Mode Register (offset: 0x2400)” on page 362).
60. Enable the send data initiator functional block. Set the Enable bit in the Send Data Initiator Mode register
(see “Send Data Initiator Mode Register (offset: 0xC00)” on page 345).
61. Enable the send BD initiator functional block by setting the Enable and Attn_Enable bits in the Send BD
Initiator Mode register (see “Send BD Initiator Mode Register (offset: 0x1800)” on page 353).
62. Enable the send BD selector functional block by setting the Enable and Attn_Enable bits in the Send BD
Selector Mode register (see “Send BD Ring Selector Mode Register (offset: 0x1400)” on page 351).
63. Enable the transmit MAC by setting the Enable bit and the Enable_Bad_TxMBUF_Lockup_fix bit in the
Transmit MAC Mode register (see “Transmit MAC Mode Register (offset: 0x45C)” on page 319
). Optionally,
the software may set the Enable_Flow_Control to enable 802.3x flow control.
64. Delay 100 microseconds.
65. Enable the receive MAC. Set the Enable bit in the Receive MAC Mode register (see “Receive MAC Mode
Register (offset: 0x468)” on page 322). Optionally, the software may set the following bits:
• Enable_Flow_Control bit–Enable 802.3x flow control
• Accept_oversized bit– Ignore RX MTU up to 64K maximum size
• Promiscuous_Mode bit–Accept all packets regardless of destination address
• No_CRC_Check bit–RX MAC will not check Ethernet CRC
• Various Hash Enable bits–if using RSS mode (Receive Side Scaling)
66. Delay 10 microseconds.
67. Setup the LED Control Register (0x40C). The Broadcom driver uses a value of 0x800 when initializing this
register.
68. Activate link and enable MAC functional blocks by setting the Link_Status bit in the MI Status register (see
“MII Status Register (offset: 0x450)” on page 318) to generate a link attention.
69. Optionally, disable auto-polling on the management interface (see “MII Mode Register (offset: 0x454)” on
page 318).
70. Set Low Watermark Maximum Receive Frame register (offset: 0x504) to a value of 1 for the BCM5717 and
BCM 5718 family of controllers.
71. Configure D0 power state in PMSCR (see “Power Management” on page 188). Note that the PMCSR
register is reset to 0x00 after chip reset. Software may optionally reconfigure this register if the device is
being moved from D3 hot/cold.
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