Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Wake on LAN Mode/Low-PowerBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 222
7. Enable the Wake_On_LAN bit in the AUXILIARY Control Register.
8. For Interesting Packet WOL Only: Set up the Interesting Packet pattern in Ethernet controller local memory.
9. For Interesting Packet WOL Only: Write a pointer value to the “WOL Pattern Pointer Register (offset: 0x430)”
on page 316. This register uses a normalized pointer value, not a device base address. The value written to
this register is BCM5700_BASE_ADDR/8. The base address must be a specific location in local memory:
0x8000, 0xC000, or 0xD000. The choice of memory location depends upon other MAC configurations, and
the selection is not arbitrary.
10. For Interesting Packet WOL Only: Write the Offset field in the “WOL Pattern Configuration Register (offset:
0x434)” on page 316. The WOL pattern checker will position into received frames on two-byte intervals. The
pattern checker compares two bytes in parallel, so host software should program the offset field accordingly.
Host software may perceive this unit as OFFSET_BYTE/2 units.
11. For Interesting Packet WOL Only: Write the Length field in the “WOL Pattern Configuration Register (offset:
0x434)” on page 316. The length value is specified in terms of Memory Arbiter clock cycles, not bytes/words/
dwords. A comprehensive discussion of how the clock cycles are calculated will be presented.
12. Set the Port_Mode field in the “EMAC Mode Register (offset: 0x400)” on page 310 to GMII mode. These bits
enable the GMII between the MAC and internal PHY.
13. For Interesting Packet WOL Only: Enable the ACPI_Power-On bit in the “EMAC Mode Register (offset:
0x400)” on page 310. This bit will enable logic for D3 hot/cold transitions to D0 ACPI state. The MAC will
also be capable of asserting PME on the PCI bus.
14. For Interesting Packet WOL Only: Enable the Magic_Packet_Detection bit in the “EMAC Mode Register
(offset: 0x400)” on page 310. The WOL logic will compare RX frames for Magic Packet patterns.
15. Set the RX RISC_Clock_Disable bit in the PCI Clock_Control register (see “Power Management Control/
Status Register (offset: 0x4C)” on page 279). The receive CPU will be stopped, and the clocking circuitry
disabled.
16. Set the Enable_Alternate_Clock bit in the PCI Clock_Control register. The Ethernet controller’s 133 MHz
Phase Locked Loop (PLL) no longer clocks internal logic and an alternate clock reference is used. Set the
PLL LowPowerClock bit while keeping the Enable_Alternate_Clock bit set. Wait at least 27 µs and then clear
the Enable_Alternate_Clock bit. The Ethernet controller’s PLL is then switched to its lower power
consumption mode.
17. In NIC applications, switch from VMAIN to VAUX in order to prevent a GRC reset. Set the required GPIOs
of Ethernet controller if any of them are used for switching the power from VMAIN to VAUX.
18. Enable the RX MAC by setting the Enable bit of “Receive MAC Mode Register (offset: 0x468)” on page 322”
and put it in promiscuous mode by setting the Promiscuous Mode bit of “Receive MAC Mode Register (offset:
0x468)” on page 322.
19. Enable the PME bit in the PCI Power Management Control/Status Register (offset: 0x4C) (see “Power
Management Control/Status Register (offset: 0x4C)” on page 279). The Ethernet controller asserts PME to
wake up the system. Set the Power_State bits to D3 in the PCI Power Management Control/Status Register
(offset: 0x4C).

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General

Brand	Broadcom
Model	NetXtreme/NetLink BCM5718 Series
Category	Controller
Language	English