MSI-X PlumbingBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 261
End of Rx Stream Debounce
Count
15:0 RW 0x000F This field is meaningful only when
0x3C00[29] is 1.
After completing the DMA of every Return
BD to the Host memory, a hardware FSM
checks if the Rx-MBUF is empty
(discounting the effects of pre-allocation). If
it is, hardware starts counting down a count
value programmed by this field. While the
count down is in progress, if another Rx
packet starts to pour into the Rx-MBUF, the
FSM goes back to idle. However if no other
Rx packet arrives, it allows the counter to
go down to zero, at which point the FSM
triggers an interrupt/MSI-X. The counter
basically de-bounces effects of IPG or
short gaps among packets within a burst.
The counter counts in Core-Clocks.
Name Bits Access
Default
Value
DESCRIPTION
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