PCI Configuration RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 272
Reserved 18:16 RO 0x0 These bits are reserved and tied low per the PCIE
specification.
Reserved 15:11 RO 0x00 These bits are reserved and tied low per the PCIE
specification.
Interrupt Disable 10 RW 0x0 When this bit is set, function is not permitted to generate
IntX interrupt messages (deasserted) regardless of any
internal chip logic. Setting this bit has no effect on the
INT_STATUS bit below. Writing this bit to 0 will un-mask
the interrupt and let it run normally.
Fast Back-to-back
Enable
9 RO 0x0 Does not apply to PCIE
System Error
Enable
8 RW 0x0 When set, this bit enables the non fatal and fatal errors
detected by the function to be reported to the Root
Complex. The function reports such errors to the Root
Complex if it is enabled to do so either through this bit or
though PCI express specific bits in DCR
Stepping Control 7 RO 0x0 Does not apply to PCIE
Parity Error Enable 6 RW 0x0 This bit enables the write to the Master data parity error
status bit. If this bit is cleared, the master data parity error
status bit will never be set.
VGA Palette
Snoop
5 RO 0x0 Does not apply to PCIE
Memory Write and
Invalidate
4 RO 0x0 Does not apply to PCIE
Special Cycles 3 RO 0x0 Does not apply to PCIE
Bus Master 2 RW 0x0 This bit controls the enabling of the bus master activity by
this device. When low, it disables an Endpoint function
from issuing memory or IO requests. Also disables the
ability to issue MSI messages.
Memory Space 1 RW 0x0 This bit controls the enabling of the memory space. When
disabled, memory transactions targeting this device return
completion with UR status
I/O Space 0 RO 0x0 This bit indicates that the device does not support I/O
space access because it is zero and can not be modified.
IO transactions targeting this device return completion
with UR status.
Name Bits Access
Default
Value
Description
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