PCI Configuration RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 284
Reserved 28:2 RO 0x00 –
DMA write watermark 21:19 RW 7 Watermark for DMA write.
0: 32B
1: 64B
2: 96B
3:128B
4:160B
5:192B
6:224B
7:256B
Reserved 18:8 RW 0 –
Enable MSIX fix 7 RW 0 Enable msi/msix legacy fix.
DMA read MRRS for slow
speed
6:4 RW 0 This setting is for 10/100M Ethernet DMA read
MRRS. The pcie_core will accord to this value to
be max DMA read length. This configuration has
no effect for GIGA mode.
0: 1024B
1: 128B
2: 256B
3: 512B
4:512+256B
5:1024+512B
6:2048B
7:4096B
Reserved 3:2 RW 0 –
Disable_64B_cache_alignment 1 RW 0 Disable 64B cache alignment for DMA write to
Host memory
Disable_32B_cache_alignment 0 RW 0 Disable 32B cache alignment for DMA write to
Host memory
Name Bits Access
Default
Value
Description
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