Ethernet MAC (EMAC) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 323
RSS IPV4 Hash Enable 16 RW 0 When this bit is set, 2-tuple hashes are enabled
for IPV4 packets.
Reserved 15:13 RO 0 –
FIX EMAC drops a packets if
incoming DA partial match
both perfect and Pause
Multicast address
12 RW 0 This bit disables the fix that EMAC stage fsm
drops a packet if incoming packet's DA has a
partial match in both perfect match address and
Pause Multicast address.
Filter Broadcast 11 RW 0 When set, reception of broadcast frames is
disabled
Keep VLAN Tag Diag mode 10 RW 0 If set, forces Receive MAC to keep the VLAN tag
in the frame.
This is for debugging purpose only and should be
reset during normal operation
No CRC Check 9 RW 0 When set, no CRC check by receive MAC on
incoming frames.
Also, allows the reception of packets received
with RXERR on MII/GMII.
Promiscuous mode 8 RW 0 When set, no source address or MC hashing
checking will be performed on incoming frames.
All frames will be accepted.
Length Check 7 RW 0 If set, 802.2 length checking is done on LLC
frames.
Accept Runts 6 RW 0 If set, MAC accepts packets less than 64 bytes.
Reserved 5 RO 0 –
Keep Pause 4 RW 0 If set, MAC forwards pause frame to host buffer.
Reserved 3 RO 0 –
Enable Flow Control 2 RW 0 Enable automatic processing of 802.3x flow
control frames.
This bit is orthogonal to the Keep Pause bit.
Enable 1 RW 0 This bit controls whether the Receive MAC state
machine is active or not.
When set to 0, it completes the current operation
and cleanly halts. Until it is completely halted, it
remains 1 when read.
Reset 0 RW 0 When this bit is set to 1, the Receive MAC state
machine will be reset.
This is a self-clearing bit.
Name Bits Access
Default
Value
Description
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