Central Power Management Unit (CPMU) RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 377
Legacy Timer Enable 18 RW 0x0 This bit controls “cpmu_legacy_timer_enable”
output.
1: Enable
0: Disable
Frequency Multiplier Enable /
Disable
(Reserved for BCM5719)
17 RW 0x1 for
BCM5717
and
BCM5718
0x0 for
BCM5719
1: Enable
0: Disable
GPHY 10 MB Receive Only
mode Enable
16 RW 0x0 Enables GPHY 10 MB Receive Only mode when
this bit is set to 1.
Reserved 15 RW 0x0 –
Link Speed Power mode
Enable
14 RW 0x0 Enable clock adjustment based on the link speed
in mission mode.
Reserved 13 DC 0x0 –
Reserved 12:11 RW 0x0 –
Link Aware Power mode
Enable
10 RW 0x0 Link Aware Power mode Enable.
1: Enable
0: Disable
Link Idle Power mode Enable 9 RW 0x0 Link Idle Power mode Enable.
1: Enable
0: Disable
Reserved 8:6 RW 0x0 –
APE Deep Sleep mode Enable 5 RW 0x0 Enable APE deep sleep power management
mode.
APE Sleep mode Enable 4 RW 0x0 Enable APE sleep power management mode.
Reserved 3 RW 0x0 –
Power-down 2 RW 0x0 Legacy Address: 0x6804:[20]
Force CPMU into Low Power State, LAN function
will be powered down (GPHY, PCIE, APE).
This bit is cleared by a rising edge of PERST_L.
CPMU Register Software
Reset
1 RW SC 0x0 Software reset for resetting all the registers to
default.
CPMU Software Reset 0 RW SC 0x0 Software reset for all the CPMU logic expect for
registers.
Name Bits Access
Default
Value
Description